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author | Carlo Zancanaro <carlo@pc-4w14-0.cs.usyd.edu.au> | 2012-10-15 17:10:06 +1100 |
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committer | Carlo Zancanaro <carlo@pc-4w14-0.cs.usyd.edu.au> | 2012-10-15 17:10:06 +1100 |
commit | be1de4be954c80875ad4108e0a33e8e131b2f2c0 (patch) | |
tree | 1fbbecf276bf7c7bdcbb4dd446099d6d90eaa516 /clang/test/CodeGen/mips-constraint-regs.c | |
parent | c4626a62754862d20b41e8a46a3574264ea80e6d (diff) | |
parent | f1bd2e48c5324d3f7cda4090c87f8a5b6f463ce2 (diff) |
Merge branch 'master' of ssh://bitbucket.org/czan/honours
Diffstat (limited to 'clang/test/CodeGen/mips-constraint-regs.c')
-rw-r--r-- | clang/test/CodeGen/mips-constraint-regs.c | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/clang/test/CodeGen/mips-constraint-regs.c b/clang/test/CodeGen/mips-constraint-regs.c new file mode 100644 index 0000000..075be05 --- /dev/null +++ b/clang/test/CodeGen/mips-constraint-regs.c @@ -0,0 +1,44 @@ +// RUN: %clang -target mipsel-unknown-linux -ccc-clang-archs mipsel -S -o - -emit-llvm %s + +// This checks that the frontend will accept inline asm constraints +// c', 'l' and 'x'. Semantic checking will happen in the +// llvm backend. Any bad constraint letters will cause the frontend to +// error out. + +int main() +{ + // 'c': 16 bit address register for Mips16, GPR for all others + // I am using 'c' to constrain both the target and one of the source + // registers. We are looking for syntactical correctness. + int __s, __v = 17; + int __t; + __asm__ __volatile__( + "addi %0,%1,%2 \n\t\t" + : "=c" (__t) + : "c" (__s), "I" (__v)); + + // 'l': lo register + // We are making it clear that destination register is lo with the + // use of the 'l' constraint ("=l"). + int i_temp = 44; + int i_result; + __asm__ __volatile__( + "mtlo %1 \n\t\t" + : "=l" (i_result) + : "r" (i_temp) + : "lo"); + + // 'x': Combined lo/hi registers + // We are specifying that destination registers are the hi/lo pair with the + // use of the 'x' constraint ("=x"). + int i_hi = 3; + int i_lo = 2; + long long ll_result = 0; + __asm__ __volatile__( + "mthi %1 \n\t\t" + "mtlo %2 \n\t\t" + : "=x" (ll_result) + : "r" (i_hi), "r" (i_lo) + : ); + return 0; +} |